EEEEK! Something WickeD This Way Comes…


There was a fairly significant design flaw in the first rev of the Serial NVM boards regarding the manner in which the chip select (CS) signals were asserted by the MCP23S08 IO expander chip.  This design flaw came to light after I took a mental “break” from the project while waiting for the boards to arrive in the mail from OSH Park.  The issue was realized literally as I was opening the mail pouch.

So, rev 2 was implemented…?  What’s going on now…?

So, rev 2 added two quad NAND chips to ensure all CS signals to the memory chips were released whenever the CS signal to the IO expander was asserted. Also, whenever the CS signal to the IO expander was released, any IO expander output in the “low” state would cause the corresponding CS signal of the memory chip to be asserted. In the process of making these changes it was also realized that pullup resistors should be added to each IO of the IO expander to prevent any IO from being in an indeterminate state after a power-up or a reset.

Great!  Off to the races again.  Well, as can be seen from the main image of this blog posting, there is a dangling net feeding into one of the NAND gate inputs…  

I had already submitted my gerbers to OSH Park a few days prior and gotten a response that the panels had been sent to the fabricator. As I saw this in the KiCAD’s eeschema, I was thinking “wait did I accidentally delete this net before or after I completed the design changes? I ran the ERC didn’t I?  I don’t remember getting any errors…?  Hmmm…  Let me check the layout.  Oh no… 🙁  GP0 has a trace to the pullup, but that net didn’t get tied to the NAND input!”

Tracing back my design flow migrating from rev 1 to rev 2, I had made use of an internally-bussed resistor network for the pullup resistors.  Everything was good in the rev 2 schematic, however when I got down to the final few PCB trace routes, it was going to greatly simplify the layout if I could swap, or reverse, 4 of the pins on the resistor network. In other EDA packages I’ve used in the past (Mentor Graphics Pads, and even EagleCAD) there is a handy feature called “Swap pins” commonly used for logic gates and various other parts for doing just this.  Well KiCAD is behind the ball on this one, or at least I didn’t see this feature, so I did it the manual way – go back to the schematic, make the changes, and then push these back through to the layout through the netlist.  Well, in doing this, I apparently severed the net shown in the pic and didn’t see it to reconnect it.  Nor, apparently, did I re-run the ERC in eeschema or it would have caught this.

So going from this (below left) ……………………………… this (below right)…

Resulted in this:
So here we are.  Rev 3 was completed tonight to solve what is hopefully the last of the issues with this oh-so-simple board design.  I plan to run a jumper on the 3 rev 2 boards I already received from OSH Park.  Once firmware is proven out I may order rev 3, which is currently up-to-snuff and ready.  Eventually these will be rolled into a LaunchPad BoosterPack form-factor and an Arduino form-factor.

Regarding firmware, I did complete a first draft of an Arduino library for the MCP23S08 with several example sketches highlighting various library functions/methods.  Download it here.  Yet to be tested functionality is the interrupt capability of the IO expander, which is not utilized in this board design, so very low priority on this.  However, provisions were made in the layout for adding a fly wire to the interrupt pin purely for experimentation of the MCP23S08 alone and in no way related to the memory functionality of the board.  

Hopefully soon to come is the next layer of firmware which makes the multiple chips accessible as one continuous array of memory to the application (the “sketch” in the case of the Arduino platform).

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